1. Field of the Invention
The present invention relates to a thin film transistor and a display device, and more particularly, to an inverted staggered thin film transistor and a display device that include a microcrystalline semiconductor film.
2. Description of Related Art
Liquid crystal display devices (LCDs), which are an example of flat panels, have advantages including low power consumption, compactness, and lightweight. The LCDs have been widely used as monitors for personal computers, portable information terminal devices, car navigation systems, and the like. In recent years, the LCDs have been widely used also as television monitors, and have replaced conventional cathode-ray tubes. Meanwhile, organic EL (Electro-Luminescence) display devices, which are superior in view angle, contrast, and responsiveness, have been vigorously developed as a next-generation flat panel.
In such display devices, a thin film transistor (TFT) that uses a semiconductor made of amorphous silicon for a channel layer has been used as a switching element for each display pixel. As examples of the structure of the TFT, MOS (Metal Oxide Semiconductor) structures such as a coplanar structure and a staggered structure are widely used. In the coplanar structure, a gate electrode and source/drain electrodes are disposed on the same side with respect to an amorphous silicon layer. In the staggered structure, the gate electrode and the source/drain electrode are disposed on different sides with respect to the amorphous silicon layer. Accordingly, in the staggered structure, the gate electrode and the source/drain electrodes are opposed to each other with the amorphous silicon film interposed therebetween. Examples of the staggered structure are classified into a top gate (forward staggered) type and a bottom gate (inverted staggered) type depending on the arrangement of the gate electrode with respect to the amorphous silicon layer.
In order to achieve a narrower frame and cost reduction of liquid crystal display devices and organic EL display devices, a display device having an integrated driving circuit in which the driving circuit such as a source driver or a gate driver using a TFT is formed on the same substrate as a pixel portion has been developed. The formation of the driving circuit on the same substrate as the pixel portion leads to a reduction in cost of an external IC. In addition, it is not necessary to provide a mounting area for the chip, resulting in a reduction in area of the frame.
A higher drive voltage is continuously applied to a driving TFT within the driving circuit for a longer period of time, as compared with a pixel TFT for pixel switching. This results in considerable deterioration in electrical characteristics. In view of this, there is proposed a TFT in which microcrystalline silicon is used as a silicon thin film of a channel layer. The TFT (microcrystalline silicon TFT) in which microcrystalline silicon is formed in a channel portion has such features that a temporal change in threshold voltage (Vth) of the TFT is small and deterioration in electrical characteristics is suppressed as compared to a TFT (amorphous silicon TFT) having amorphous silicon formed therein.
Examples of a method of forming microcrystalline silicon include a method of crystallizing, by laser annealing, amorphous silicon deposited by a plasma CVD method, and a method of direct deposition by the plasma CVD method. However, the manufacturing process for crystallization by laser annealing using an excimer laser or the like is complicated, which makes it difficult to achieve downsizing and cost reduction. For this reason, researches have been conducted to directly deposit microcrystalline silicon by the plasma CVD method.
When microcrystalline silicon (microcrystalline Si) is deposited using the plasma CVD method, it is important to improve the crystallization rate by removing an amorphous layer called an incubation layer at the initial stage of deposition. Particularly in an inverted staggered TFT, which can be produced with a small number of processes and is excellent in terms of mass production, a microcrystalline Si layer is formed on a gate insulating film. Accordingly, it is necessary to remove the incubation layer. This is because if an uncrystallized incubation layer is formed, the characteristics of a channel portion are deteriorated.
Methods for improving the crystallization rate by reducing the incubation layer are disclosed in Japanese Unexamined Patent Application Publications Nos. 2007-221137 and 2009-117405, for example. Japanese Unexamined Patent Application Publication No. 2007-221137 discloses that the crystal size uniformity of microcrystalline Si is improved by carrying out a plasma process on the gate insulating film by using SiF4 or SiF4—H2 gas. Additionally, Japanese Unexamined Patent Application Publication No. 2009-117405 discloses a method in which the crystallinity of microcrystalline Si is improved by forming crystal nuclei on an insulating film using SiF4 and SiH4 gases and by further forming a microcrystalline Si layer using a deposition gas in place of the SiF4 and SiH4 gases.
However, as the incubation layer is reduced to improve the crystallization rate, another problem occurs. Particularly in the inverted staggered TFT in which a silicon nitride film is used as a gate insulating film, there arises a problem that a threshold of the TFT becomes a negative value as the incubation layer is reduced to improve the crystallization rate. The TFT having a negative threshold voltage (Vth) shows a characteristic of a considerable offset to the negative side in a curve (Id−Vg characteristic curve) showing characteristics of a gate voltage (Vg) and a source-drain current (Id).
FIG. 14 is a graph showing an Id−Vg characteristic curve in a linear region of a microcrystalline silicon TFT of the related art when the threshold is a negative value. Referring to FIG. 14, the Id−Vg curve of the microcrystalline silicon TFT of the related art when the threshold is a negative value is indicated by a dashed line, and the Id−Vg curve of an amorphous silicon (a-Si) TFT is indicated by a solid line. The Id−Vg curve shown in FIG. 14 is standardized by voltage-current characteristics of an a-Si TFT. As is seen from FIG. 14, the microcrystalline silicon TFT obtained when the threshold is a negative value shows a characteristic of a considerable offset to the negative side, as compared with the a-Si TFT. As is obvious from FIG. 14, even when no voltage is applied to the gate electrode (Vg=0 V), a current at a level of 1/10 of an ON-state current flows.
When the microcrystalline silicon TFT having a negative threshold is used as a driving TFT, a current constantly flows therethrough and a circuit operation failure occurs due to the circuit configuration. Meanwhile, in the a-Si TFT, almost no current flows when Vg=0 V, there is no problem with the circuit operation. However, the a-Si TFT cannot be used as a driving TFT because of its low mobility. On the other hand, when the microcrystalline silicon TFT having a negative threshold is used as a pixel TFT for pixel switching, a negative offset does not pose any problem depending on the degree of offset. This is because the pixel TFT is turned on and off using a gate voltage (Vgh) during ON period and a gate voltage (Vgl) during OFF period. Accordingly, if the voltages Vgh and Vgl are shifted by the offset amount, the microcrystalline silicon TFT having a negative threshold can also be used as a pixel TFT.
The reason that the threshold of the inverted staggered TFT in which the silicon nitride film (SiN film) is used as the gate insulating film is considerably offset to the negative side seems to be as follows. Si—N bonds on the surface of the SiN film are broken by plasma upon deposition of microcrystalline Si. Then, nitrogen separated from the bonds enters the silicon crystal site during the process of forming microcrystalline Si, and acts as an n-type impurity (pentavalent), thereby generating free electrons.
FIG. 15 shows a profile representing a concentration distribution of oxygen and nitrogen measured by SIMS (Secondary Ion Mass Spectrometry) of the microcrystalline silicon TFT of the related art when the threshold is a negative value. Note that in FIG. 15, the nitride film indicates an SiN film formed as a gate insulating film, uc-Si indicates a microcrystalline silicon layer formed on the gate insulating film, a-Si indicates an amorphous silicon layer formed on the microcrystalline silicon layer and n-type a-Si indicates an ohmic contact layer formed on the amorphous silicon layer. As is clear from the profile representing the concentration distribution shown in FIG. 15, nitrogen (N) is diffused in the microcrystalline Si, and the concentration of nitrogen decreases as the distance from the nitride film. The diffusion of nitrogen defined herein indicates a curved portion (portion at which the slope is varied) of the profile as shown in FIG. 15.
Normally, the nitrogen impurity concentration in microcrystalline Si is preferably in the range of 1×1018 cm−3 to 3×1018 cm−3. When the above-mentioned problem occurs, however, the nitrogen concentration in the microcrystalline Si adjacent to the SiN film reaches a level of dozens of times the normal level. It is generally known that when microcrystalline Si is deposited without doping any impurities, the microcrystalline Si does not show a fully intrinsic property due to a defect of the silicon structure or the like, but exhibits a slight n-type characteristic. When the diffusion of nitrogen occurs, a relatively strong n-type characteristic is exhibited in the vicinity of the interface with the SiN film of microcrystalline Si, which facilitates formation of a channel. Thus, the Id−Vg characteristic (threshold) is offset to the negative side.
In the inverted staggered TFT, such a considerable offset to the negative side in the Id−Vg characteristic may not occur when an a-Si layer is stacked on the microcrystalline Si so as to reduce an OFF-state current. However, this is because a current Ids itself hardly flows due to an energy barrier caused by a bandgap difference between the microcrystalline Si layer and the a-Si layer or due to a high resistance layer caused by a defect in an interface portion, and thus a higher gate voltage Vg is required. Therefore, the above-mentioned problem becomes more remarkable in the TFT in which the interface resistance is reduced and the current Ids normally flows.
To solve the problem of the negative offset of the threshold voltage, it is possible to suppress the diffusion of N impurities into the microcrystalline Si. As a method for suppressing the diffusion of N impurities into the microcrystalline Si, a method of applying an oxide film to the gate insulating film can be employed. However, since the oxide film has a low dielectric constant, it is necessary to reduce the thickness of the gate insulating film to optimize the capacitance of the insulating film. The reduction in thickness of the gate insulating film causes a decrease in dielectric voltage and deterioration in particle coatability at the time of deposition, and further causes defects due to these factors. This results in deterioration in production yield. Further, the fermi level of the microcrystalline Si formed on the oxide film tends to be shifted to the valence band side. This results in an increase of the threshold voltage. Thus, when the oxide film is used as the gate insulating film, the TFT characteristics are deteriorated compared to the case where a nitride film is used.
Furthermore, when the oxide film is applied to the gate insulating film, there is another problem in that an optical leak current increases. The term “optical leak current” refers to a current generated when electron-hole pairs which are generated when light is incident on microcrystalline Si and a-Si stacked thereon flow through a silicon layer. In the microcrystalline Si in which the hole mobility is increased by crystallization, this optical leak current is liable to flow, and the degree of the optical leak current increases when the oxide film is used as the gate insulating film. The reason for this seems that the level acting as an acceptor level is generated on the valence band side in the microcrystalline Si formed on the oxide film, since the fermi level is shifted to the valence band side. For this reason, the TFT that suppresses the diffusion of N impurities into the microcrystalline Si by applying the oxide film to the gate insulating film is not suitable for a liquid crystal display device that irradiates the TFT with backlight, and cannot be used as a transistor for pixel switching.
To solve the problem of the negative offset of the threshold voltage, it is also possible to add a minute amount of p-type impurities to microcrystalline Si. For example, Japanese Unexampled Patent Application Publication No. 10-189977 discloses a technique in which microcrystalline Si is made intrinsic by adding a minute amount of B2H6 gas. Additionally, Japanese Unexamined Patent Application Publication No. 2009-117405 discloses a technique in which a silicon layer is formed by adding B2H6 and BF3 and the concentration of boron contained in the silicon layer is set in the range of 1×1014 cm−3 to 6×1016 cm−3. Also,
Japanese Unexampled Patent Application Publication No. 2009-055011 discloses a technique in which p-type or n-type impurities are added to silicon.